1. Field of the Invention
The present invention relates to a method, system, and article of manufacture for executing multiple threads in a processor.
2. Description of the Related Art
An operating system scheduler may assign specific timeslices on a processor to various threads. The operating system scheduler, on a regular basis, saves the state of a thread and replaces it with another for the processor to execute. Additionally, the operating system may assign threads to execute on logical processors executed by a physical processor. A logical processor is a logical construct or entity representing processor resources that run threads. A processor alternates between executing different logical processors and their threads. In further systems, some processors may implement only a single logical processor.
An operating system scheduler may implement preemptive scheduling, where a timer interrupt is used to limit the time each thread executes. When the timer expires, such as after a few milliseconds or a number of instructions, an interrupt is generated to invoke the operating system scheduler to determine whether to interrupt the currently executing thread or allow the thread to continue executing. The processor maintains a register file including information on the thread being executed. After executing one thread for a time period, the processor calls the operating system scheduler to perform a context switch to execute a next thread. During the context switch, the operating system scheduler writes the register file of the next thread to execute to the processor and then invokes the processor to switch to executing this next thread.
This technique has the disadvantage of interrupting a thread that is entitled to continue executing for an extended period.
A non-preemptive scheduler allows threads to execute un-interrupted until completion. This technique has the disadvantage of allowing a lower priority thread or thread that is not executing properly to prevent or delay other higher priority threads from executing.
A symmetric multithreading (SMT) processor has multiple logical processors in the same central processing unit (CPU). In SMT systems, a timeslice for a thread to process a program within the hardware may extend for a few nanoseconds and a timeslice initiated by the operating system may extend for several milliseconds. Registers in the CPU include information identifying each thread and its status, e.g., executing, not executing, etc. Timers or decrementers force each thread into the operating system scheduler every few milliseconds. However, between these interrupts to the operating system scheduler, each thread may be executed on millions of shorter, hardware-managed timeslices. In prior art SMT systems, there is timeslicing at a nano level (managed by the hardware, and not involving the operating system) and another type of timeslicing at the macro level (managed explicitly by the operating system).
There is a need in the art for improved techniques for configuring a processor to execute multiple threads.